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(a) Dx (x 4 ) = Dx (x 3 x) algebra ua ub = ua+b = x 3 Dx (x) + x Dx (x 3 ) = x 3 (1) + x(3x 2 ) = x 3 + 3x 3 = 4x 3 (b) Dx (x 5 ) = Dx (x 4 x) = x 4 Dx (x) + x Dx (x 4 ) = x 4 (1) + x(4x 3 ) = x 4 + 4x 4 = 5x 4 (c) Dx ((x 3 + x)(x 2 x + 2)) = (x 3 + x) Dx (x 2 x + 2) + (x 2 x + 2) Dx (x 3 + x) = (x 3 + x)(2x 1) + (x 2 x + 2)(3x 2 + 1) [by the product rule] [by example (a)] and ua = ua b ub

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Fig. 3-15 (a) By KVL around the emitter-base loop, VEE VBEQ 4 0:7 3 IEQ 1:1 10 3

CHAP. 3]

(b) By KVL around the transistor terminals (which constitute a closed path), VCBQ VCEQ VBEQ 7 0:7 6:3 V With negligible leakage current, (3.1) gives ICQ IEQ 0:99 1:1 10 3 1:089 mA Finally, by KVL around the base-collector loop, RC VCC VCBQ 12 6:3 5:234 k ICQ 1:089 10 3

[by the product rule]

Collector characteristics for the Ge transistor of Fig. 3-15 are given in Fig. 3-16. If VEE 2 V, VCC 12 V, and RC 2 k , size RE so that VCEQ 6:4 V.

_ 10

Solved Problem 16.1 Henderson and Erin have decided to form a part nership. Henderson invests the following assets (shown at their agreed upon value) and he also transfers liabilities to the new rm.

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The reader may have noticed a pattern in the derivatives of the powers of x: Dx (x) = 1 = 1 x 0 Dx (x 2 ) = 2x Dx (x 3 ) = 3x 2 Dx (x 4 ) = 4x 3 Dx (x 5 ) = 5x 4

_ 12

_ 14

This pattern does in fact hold for all powers of x. RULE 4. Dx (x n ) = nx n 1 where n is any positive integer. For a proof, see Problem 12.2. EXAMPLES

_ 16

_ 18

Dx 1 3 3 x 4x 2 + 2x 5 2 = Dx = 3 3 1 x Dx (4x 2 ) + Dx (2x) Dx 5 2 [by Rule 1] [by Rule 2 and Corollary 12.2] [by Rule 4]

_ 20

Henderson s Accounts Cash Accounts Receivable Merchandise Inventory Equipment Accounts Payable Notes Payable Value $17,500 7,000 10,000 4,200 3,500 3,600

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Fig. 3-16 We construct, on Fig. 3-16, a dc load line having vCB intercept VCC 12 V and iC intercept VCC =RC 6 mA. The abscissa of the Q point is given by KVL around the transistor terminals: VCBQ VCEQ VBEQ 6:4 0:3 6:1 V With the Q point de ned, we read IEQ 3 mA from the graph. leads to RE Now KVL around the emitter-base loop

3 Dx (x 3 ) 4 Dx (x 2 ) + 2 Dx (x) 0 5 3 = (3x 2 ) 4 (2x) + 2 (1) 5 9 = x 2 8x + 2 5

The circuit of Fig. 3-17 uses current- (or shunt-) feedback bias. The Si transistor has ICEO % 0, VCEsat % 0, and hFE 100. If RC 2 k and VCC 12 V, size RF for ideal maximum symmetrical swing (that is, location of the quiescent point such that VCEQ VCC =2 .

Fig. 3-17

More concisely, we have: RULE 5. To differentiate a polynomial, change each nonconstant term ak x k to kak x k 1 and drop the constant term (if any). EXAMPLES

Application of KVL to the collector-emitter bias circuit gives IBQ ICQ RC VCC VCEQ With ICQ hFE IBQ , this leads to IBQ VCC VCEQ 12 6 29:7 A hFE 1 RC 100 1 2 103 VCEQ VBEQ 6 0:7 178:5 k IBQ 29:7 10 6

For the ampli er of Fig. 3-17, CC 100 F, RF 180 k , RL 2 k , RS 100 k , VCC 12 V, and vS 4 sin 20 103 t V. The transistor is described by the default npn model of Example 3.2. Use SPICE methods to (a) determine the quiescent values (IBQ ; ICQ ; VBEQ ; VCEQ ) and (b) plot the input and output currents and voltages vS ; iS ; vL ; iL .

Erin agrees to invest $26,000 in cash. Record (a) Henderson s invest ment; (b) Erin s investment. Solution: (a) Cash Accounts Receivable Merchandise Inventory Equipment Accounts Payable Notes Payable Henderson, Capital (b) Cash Erin, Capital 17,500 7,000 10,000 4,200 3,500

(a) The netlist code that follows models the circuit:

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