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The circuit of Fig. 3-29 illustrates a method for biasing a CB transistor using a single dc source. transistor is a Si device VBEQ 0:7 V , 99, and IBQ 30 A. Find (a) R2 , and (b) VCEQ . Ans: a 3:36 k ; b 6:06 V Rework Problem 3.28(a) with R2 5 k and all else unchanged. Ans: 13:16 mA and ICQ 16:84 mA Because of a poor solder joint, resistor R1 of Problem 3.28(a) becomes open-circuited. percentage change in ICQ that will be observed. Ans: 508:5%

we may substitute in the product rule (proved in Problem 13.1) to obtain Dx f (x) g(x) = Dx f (x) = = which is the desired quotient rule. 1 g(x) = f (x)

The circuit of Problem 3-28(a) has -independent bias RE ! 10RB = Find the allowable range of if ICQ can change at most 2 percent from its value for 110 Ans: 86:4 149:7 For the circuit of Fig 3-27, vS 0:25 cos !t V; RB 30 k ; VB 1 V, and VCC 12 V The transistor is described by the default npn model If VCEsat 0 and ICBO 0, use SPICE methods to determine the range of RL for class A operation Hint: A sweep of RL values can determine the particular value of RL for which VCEQ VCC =2 (Netlist code available at author website) Ans: RL 7:74 k If an emitter resistor is added to the circuit of Fig 3-17, nd the value of RF needed to bias for maximum symmetrical swing Let VCC 15 V, RE 1:5 k , and RC 5 k .

Assume the transistor is an Si device with ICEO VCEsat 0 and 80 Ans: 477:4 k In the circuit of Fig 3-20, the Ge transistor has ICEO 0 and 50 Assume the capacitor is replaced with a short circuit Let VS 2 V; VCC 12 V; RC 4 k ; RS 100 k , and RB 330 k Find the ratios (a) ICQ =Is and (b) VCEQ =VS Ans: a 374:6; b 0:755 In the di erential ampli er circuit of Fig 3-22, the two identical transistors are characterized by the default npn model Let RB 10 k , RE RC 6:8 k , and VCC VEE 15 V Use SPICE methods to determine (a) VBEQ1 and (b) voltages vo1 vo2 (Netlist code available from author website.

f (x)Dx g(x) g(x)Dx f (x) + [g(x)]2 [g(x)]2 g(x)Dx f (x) f (x)Dx g(x) [g(x)]2

) Ans: a VBEQ1 V 4; 3 8:89 V; b vo1 vo2 V 4 V 6 8:01 V In the ampli er of Fig 3-10(a), R1 1 k ; R2 9 k ; RE 100 ; RL 1 k ; VCC 12 V; CC CE ! 1, and 100 The Si transistor has negligible leakage current, with VCEsat ICBO 0 Find RC so that vL exhibits maximum symmetrical swing Ans: 1:89 k If in Problem 331, R1 is changed to 9 k and all else remains unchanged, determine the maximum undistorted swing of ic Ans: 1:5 mA In the CC ampli er of Problem 332, let iS 10 sin !t A Calculate vL after graphically determining vCE Ans: The ac load line and vCE are sketched on Fig 3-26: vCE % 5:7 sin !t V; vL sin !t V.

4.1. INTRODUCTION The operation of the eld-e ect transistor (FET) can be explained in terms of only majority-carrier (one-polarity) charge ow; the transistor is therefore called unipolar. Two kinds of eld-e ect devices are widely used: the junction eld-e ect transistor (JFET) and the metal-oxide-semiconductor eld-e ect transistor (MOSFET).

When k is positive, this is just Rule 4 ( 12). When k = 0, Dx (x k ) = Dx (x 0 ) = Dx (1) = 0 = 0 x 1 = kx k 1 Now assume k is negative; k = n, where n is positive. algebra By de nition, 1 x k = x n = n x By (1) of Problem 13.2, Dx (x k ) = Dx 1 xn = 1 xn